In the rapid development of computers many advancements have been seen in the areas of processor speed, throughput, communications, and fault tolerance. Initially computer systems were standalone devices in which a processor, memory and peripheral devices all communicated through a single bus. Later, in order to improve performance, several processors were interconnected to memory and peripherals using one or more buses. In addition, separate computer systems were linked together through different communications mechanisms such as, shared memory, serial and parallel ports, local area networks (LAN) and wide area networks (WAN). However, these mechanisms have proven to be relatively slow and subject to interruptions and failures when a critical communications component fails.
One type of architecture of many that has been developed to improve throughput, allow for parallel processing, and to some extent, improve the robustness of a computer network is called a hypercube. Hypercube is a parallel processing architecture made up of binary multiples of computers (4, 8, 16, etc.). The computers are interconnected so that data travel is kept to a minimum. For example, in two eight-node cubes, each node in one cube would be connected to the counterpart node in the other. However, when larger numbers of processors and peripheral devices are included in the network, connecting each node, which includes processors and peripheral devices, to all other nodes is not possible. Therefore, routing tables for data must be established which indicate the shortest path to each node from any other node.
A hypercube like architecture, and many other types of networks and computer architectures, work well but are rigid in their designs. For example, if a system is needed that has ten processors in it, then one must configure the hypercube with sixteen processors. Further, no provision is made for interfacing to several local area networks, wide area networks, and different types of input/output (I/O) controllers. Therefore, hypercube may be well suited for processor intensive application, but is ill suited for a communications network.
More recently, several different types of packet switching networks have been created in order to facilitate communications amongst computer systems. Two similar packet switched systems include next generation input/output (NGIO) and InfiniBand. Both NGIO and InfiniBand are highly flexible computer architectures in which any number of computer systems may communicate to each other and to any number of local area networks, wide area networks, and peripheral devices. Both NGIO and InfiniBand utilize serial communications equipment and switches that have minimum transfer rates of up to 2.5 gigabit per second (Gbps).
However, in order to achieve a one plus Gbps transfer rate along with a highly flexible connectivity capability the communications controllers and switches must be relatively sophisticated, complex and expensive devices. In particular, these communications controllers and switches must contain multiple buffers per port to act as temporary storage areas. In order to achieve the necessary high throughput rates it is preferable that both the logic and memory required for these controllers and switches occupy a single chip. However, in order to be able to support full-duplex communication at least two memory storage areas are required. In order to fill one buffer from one port while transmitting to another port, it may be necessary to have up to four buffers in order to accomplish a simultaneous read and write. However, handling simultaneous reads and writes from different ports with different buffers being filled and emptied at different rates requires large amounts memory and significantly complex logic.
Therefore, what is needed is a device that will minimize the complexity and logic involved in performing simultaneous reads and writes to multiple ports in a packet switching network. This device should also minimize the number of buffers needed to perform simultaneous reads and writes to different ports. It should further minimize the amount of memory needed by each buffer. Further, it should try to utilize, the maximum extent possible, each buffer's memory space so that none is wasted. In addition, the logic utilized by this device should be simple and thus require the minimum amount of space on a chip. A significant cost savings should be seen using this device since the minimum amount of memory required is being utilized and the logic required also takes up the minimal amount of space on a chip. Thus, this device should enable the efficient and rapid transport of packets in a network.